The present disclosure relates to a solid-state imaging device and an electronic apparatus, in particular, to a solid-state imaging device and an electronic apparatus to achieve low noise and a high frame rate.
In recent years, CMOS (Complementary Metal Oxide Semiconductor) image sensors have been increasingly employed as an imaging device for mobile phones with an imaging function, digital still cameras, camcorders, and surveillance cameras and the like. The CMOS image sensor has a characteristic that a pixel portion and a peripheral circuit portion are formed on the same semiconductor substrate.
In the pixel portion, a number of pixels are formed in an array. Generally, a four-transistor-type pixel architecture is often employed in a pixel, which includes a transfer transistor, an amplifying transistor, a selection transistor and a reset transistor.
The transfer transistor transfers a charge accumulated in a PD (Photodiode) that is a photoelectric conversion portion and a charge accumulation portion, to an FD (Floating Diffusion) detecting the charge generated in the PD. The amplifying transistor amplifies the charge accumulated in the FD and outputs a level of signal corresponding to the charge. The selection transistor selects a pixel which is a target for signal reading, and the reset transistor resets the charge accumulated in the FD.
In addition, in order to reduce the pixel size, a three-transistor-type pixel architecture may often be employed, which includes a transfer transistor, an amplifying transistor and a reset transistor, without a selection transistor being mounted.
However, recently, corresponding to a demand for an imaging device with more pixels, smaller size and the like, the size of the pixel mounted on an imaging device has been reduced. For example, a pixel sharing structure can be employed to reduce the size of the CMOS image sensor.
In a predetermined number of the pixels (for example, two or four pixels) as a share unit, the pixel sharing structure is a pixel architecture using the FD, the amplifying transistor, the selection transistor and the reset transistor in common, and having the PD and the transfer transistor respectively. For example, a two-pixel sharing structure is formed with two pixels by using the FD, the amplifying transistor, the selection transistor and the reset transistor in common, wherein the two pixels have the PD and the transfer transistor respectively.
Accordingly, while eight transistors are used in two pixels (four transistors per pixel) in a case where the pixel sharing structure is not employed, five transistors are used in two pixels in a case where the two-pixel sharing structure is employed. In other words, the two-pixel sharing structure may have only 2.5 transistors per pixel, it is possible to reduce the area where a transistor occupies, and to increase the area of the PD.
For example, Japanese Unexamined Patent Application Publication No. 2009-26984 discloses a solid-state imaging device in which sensitivity deviation between pixels is reduced, while maintaining a high aperture ratio, by employing the pixel sharing structure.
However, in the solid-state imaging device disclosed in Japanese Unexamined Patent Application Publication No. 2009-26984, in order to suppress the sensitivity deviation between green pixels in a row in which red pixels are arranged and green pixels in a row in which blue pixels are arranged, the amplifying transistor, the selection transistor and the reset transistor are preferably included within a pixel pitch. Therefore, the gate length of the amplifying transistor is restricted by the pixel pitch. As the pixel size is reduced and the gate length of the amplifying transistor is set to be shortened, random noise of the amplifying transistor is increased and thus it is difficult to realize low noise. In this way, it is assumed that imaging properties deteriorate.
Here, an S/N ratio (signal/noise ratio) of a signal to noise is known as one of the characteristics determining image quality of the CMOS image sensor. The signal is obtained from the product of the sensitivity of the imaging device and conversion efficiency, and the noise includes a random noise or a shot noise and the like. The random noise is known as one caused by the pixels and one caused by peripheral transistors. The random noise caused by the pixels includes noise generated in the PD and noise generated in the amplifying transistor. Recently, as an embedded photodiode structure has been employed as the CMOS image sensor, the noise generated in the PD is remarkably reduced. On the other hand, the noise generated in the amplifying transistor tends to largely affect the random noise.
In addition, it is known that a 1/f noise which is a type of the random noise generated in the amplifying transistor is in inverse proportion to the product of the gate length and the gate width of the amplifying transistor. That is, in order to improve the S/N characteristic, it is effective to increase the size (gate length L×gate width W) of the amplifying transistor.
Japanese Unexamined Patent Application Publication No. 2010-165854 discloses the solid-state imaging device, which is formed by a structure having a layout using a photodiode array of two pixels in a vertical direction and 4×n pixels in a horizontal direction as one shared unit, and in which the size of the amplifying transistor is increased.
However, in the solid-state imaging device in Japanese Unexamined Patent Application Publication No. 2010-165854, it is assumed that, even though it is effective to reduce the 1/f noise by increasing the size of the amplifying transistor, it is difficult to cope with speeding-up of a frame rate. That is, in the pixel sharing structure which shares the pixels arranged in a horizontal direction intersecting a direction of signal lines which read out the signals from the pixels, since it is difficult to perform a signal process at the following stage until the reading of the signals is completed from the plurality of columns sharing the pixels, pixel signal reading speed is restricted. Therefore, it is difficult to realize a high frame rate in the pixel sharing structure sharing the pixels in the horizontal direction.